The disclosure relates to a memory controller, a memory system, and a method of operating the same, and more particularly, to a memory controller managing a temperature of a memory device upon a training operation for the memory device, a memory system, and a method of operating the same.
Memory devices, which are widely used for high-performance electronic systems, have increasingly higher capacity and speed. As an example of the memory devices, a dynamic random access memory (DRAM), which is a volatile memory, is a memory determining data by a charge stored in a capacitor.
DRAMs have yield issues due to shrunk fabrication processes for accomplishing higher integration rates. For increasing a yielding rate, DRAMs are typically determined as passing or failing through wafer level testing or package level testing.
In various test processes, training is performed for determining optimal operating parameters of the DRAMs and operation margins are set using the optimal operating parameters in normal operation of the DRAMs. For example, during booting-up operation of a memory system, an idle state of the memory system, or the like, a training operation is conducted for optimizing set-up/hold time-related parameters of commands, data, and the like for a memory device. Here, as a result of conducting the training operation, the optimized parameters are applied upon conducting a normal operation of the memory system. Here, there may be a difference between a temperature of the memory device upon conducting the training operation and a temperature of the memory device upon conducting the normal operation. Along with higher speed and higher integration of a training memory system, set-up/hold time of commands, data, and the like absolutely decreases. Thus, since there occur distortion and shift of commands, data, and the like due to a temperature, the parameters optimized as a result of conducting the training operation may not be suitable for conducting the normal operation of the memory system.